Performance analysis of digital delay lock loops in the presence of Doppler shift

Szu-Lin Su, Nan Yang Yen, Sheng Cheng Hsieh

研究成果: Paper

摘要

This paper considers discrete time analyses of first- and second-order digital delay lock loops (DDLL), and presents the results of an investigation concerning the performance degradation due to Doppler. The performance measures evaluated include the steady-state timing error probability density function (pdf) and the mean time to lost lock. The measures are characterized in terms of the Doppler shift and the loop signal-to-noise ratio. Moreover, approximate expressions for the steady-state timing error probability density and the mean time to lose lock are also presented for the first- and second-order digital delay lock loops. The analyses are confirmed by numerical results and simulation.

原文English
頁面1896-1900
頁數5
出版狀態Published - 1995 一月 1
事件Proceedings of the 1995 IEEE International Conference on Communications. Part 1 (of 3) - Seattle, WA, USA
持續時間: 1995 六月 181995 六月 22

Other

OtherProceedings of the 1995 IEEE International Conference on Communications. Part 1 (of 3)
城市Seattle, WA, USA
期間95-06-1895-06-22

    指紋

All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications
  • Electrical and Electronic Engineering

引用此

Su, S-L., Yen, N. Y., & Hsieh, S. C. (1995). Performance analysis of digital delay lock loops in the presence of Doppler shift. 1896-1900. 論文發表於 Proceedings of the 1995 IEEE International Conference on Communications. Part 1 (of 3), Seattle, WA, USA, .