Performance-directed compaction for VLSI symbolic layouts

Lih Yang Wang, Yen Tai Lai, Bin Da Liu, Tin Chung Chang

研究成果: Article同行評審

摘要

An effective approach for circuit performance improvement in VLSI symbolic layout compaction is presented. The approach is different from traditional approaches which aim at minimizing the total wire length; it directly optimizes the length of critical synchronous paths. Moreover, the critical synchronous paths are optimized before the layout size is minimized. The problem is so complicated that graph-theoretical algorithms for the general compaction problem cannot be used. Therefore, a new algorithm which consists of a graph-based technique and the simplex algorithm is proposed for the problem. Experimental results show that this algorithm is quite efficient.

原文English
頁(從 - 到)65-74
頁數10
期刊Computer-Aided Design
27
發行號1
DOIs
出版狀態Published - 1995 一月

All Science Journal Classification (ASJC) codes

  • 電腦科學應用
  • 電腦繪圖與電腦輔助設計
  • 工業與製造工程

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