Performance-driven analog placement considering boundary constraint

Cheng Wu Lin, Jai Ming Lin, Chun Po Huang, Soon Jyh Chang

研究成果: Conference contribution

23 引文 斯高帕斯(Scopus)

摘要

To reduce parasitic mismatches in analog design, we usually care about the property of symmetric placement for symmetry groups,which would form several symmetry islands in a chip. However, routing is greatly affected by placement results. If modules with nput or output ports are placed arbitrarily in a symmetry island, the routing wires, which connect these modules with other modules outside the island, may induce unwanted parasitics coupling to signals, and thus circuit performance is deteriorated. This phenomenon can not be identified by a cost function, which only considers placement area and total wire length. Therefore, we would like to introduce the necessity of considering boundary constraint for the modules with input or output ports in symmetry islands. Based on ASF-B* tree [3], we explore the feasible conditions for 1D and 2D symmetry islands to meet this constraint. Further, a procedure is presented to maintain the easibility for each ASF-B* tree after perturbation. Experimental results show that our approach guarantees the boundary property for the modules with input or output ports in symmetry islands.

原文English
主出版物標題Proceedings of the 47th Design Automation Conference, DAC '10
頁面292-297
頁數6
DOIs
出版狀態Published - 2010
事件47th Design Automation Conference, DAC '10 - Anaheim, CA, United States
持續時間: 2010 6月 132010 6月 18

出版系列

名字Proceedings - Design Automation Conference
ISSN(列印)0738-100X

Other

Other47th Design Automation Conference, DAC '10
國家/地區United States
城市Anaheim, CA
期間10-06-1310-06-18

All Science Journal Classification (ASJC) codes

  • 電腦科學應用
  • 控制與系統工程
  • 電氣與電子工程
  • 建模與模擬

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