Performance-driven placement for dynamically reconfigurable FPGAs

Guang Ming Wu, Jai Ming Lin, Yao Wen Chang

研究成果: Article同行評審

摘要

In this article, we introduce a new placement problem motivated by the Dynamically Reconfigurable FPGA (DRFPGA) architectures. Unlike traditional placement, the problem for DRFPGAs must consider the precedence constraints among logic components. For the placement, we develop an effective metric that can consider wirelength, register requirement, and power consumption simultaneously. With the considerations of the new metric and the precedence constraints, we then present a three-stage scheme of partitioning, initial placement generation, and placement refinement to solve the new placement problem. Experimental results show that our placement scheme with the new metric achieves respective improvements of 17.2, 27.0, and 35.9% in wirelength, the number of registers, and power consumption requirements, compared with the list scheduling method.

原文English
頁(從 - 到)628-642
頁數15
期刊ACM Transactions on Design Automation of Electronic Systems
7
發行號4
DOIs
出版狀態Published - 2002 10月

All Science Journal Classification (ASJC) codes

  • 電腦科學應用
  • 電腦繪圖與電腦輔助設計
  • 電氣與電子工程

指紋

深入研究「Performance-driven placement for dynamically reconfigurable FPGAs」主題。共同形成了獨特的指紋。

引用此