Performance evaluation of cache depot on CC-NUMA multiprocessors

Hung Chang Hsiao, Chung Ta King

研究成果: Paper同行評審


Cache depot is a performance enhancement technique on cache-coherent non-uniform memory access (CC-NUMA) multiprocessors, in which nodes in the system store extra memory blocks on behalf of other nodes. In this way, memory requests from a node can be satisfied by nearby depot nodes without going all the way to the home node. This not only reduces memory access latency and network traffic, but also spreads the network load more evenly. In this paper, we study the design strategy for cache depot that (1) enhances the network interface of each node to include a depot cache which stores those extra memory blocks for other nodes, and (2) employs a new multicast routing scheme, which is called the multi-hop worms and works cooperatively with depot caches, to transmit coherence messages. By considering message routing and depot caches together, the design concept can be applied even to those CC-NUMA systems that have a non-hierarchical, scalable interconnection network. We have developed an execution-driven simulator to evaluate the effectiveness of the design strategy. Performance results from using four SPLASH-2 benchmarks show that the design strategy improves the performance of the CC-NUMA multiprocessor by 11% to 21%. We have also studied in depth various factors which affect the performance of cache depot.

出版狀態Published - 1998 十二月 1
事件Proceedings of the 1998 International Conference on Parallel and Distributed Systems, ICPADS - Tainan, China
持續時間: 1998 十二月 141998 十二月 16


OtherProceedings of the 1998 International Conference on Parallel and Distributed Systems, ICPADS
城市Tainan, China

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

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