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Performance evaluation of stacked gate-all-around MOSFETs at 7 and 10 nm technology nodes

研究成果: Conference contribution

5   連結會在新分頁中打開 引文 斯高帕斯(Scopus)

摘要

Performance evaluation of stacked gate-all-around (GAA) MOSFETs on device scaling and performance benchmark against FinFETs based on scale length are presented. While stacked GAA technique provides higher current (per pitch), FinFET counterpart shows its advantage in intrinsic gate delay. Such advantage becomes even more significant toward smaller technology node. By adjusting the aspect ratio of GAA devices based on same scale length, the thinner rectangular GAA case allows more stacked layers than the square case at the same total height and hence provides higher current. However, comparable intrinsic speeds are predicted for both cases.

原文English
主出版物標題Proceedings of the 17th International Symposium on Quality Electronic Design, ISQED 2016
發行者IEEE Computer Society
頁面169-172
頁數4
ISBN(電子)9781509012138
DOIs
出版狀態Published - 2016 5月 25
事件17th International Symposium on Quality Electronic Design, ISQED 2016 - Santa Clara, United States
持續時間: 2016 3月 152016 3月 16

出版系列

名字Proceedings - International Symposium on Quality Electronic Design, ISQED
2016-May
ISSN(列印)1948-3287
ISSN(電子)1948-3295

Other

Other17th International Symposium on Quality Electronic Design, ISQED 2016
國家/地區United States
城市Santa Clara
期間16-03-1516-03-16

All Science Journal Classification (ASJC) codes

  • 硬體和架構
  • 電氣與電子工程
  • 安全、風險、可靠性和品質

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