Pipelined architecture of fast modular multiplication for RSA cryptography

Jia Lin Sheu, Ming-Der Shieh, Chien Hsing Wu, Ming Hwa Sheu

研究成果: Conference article同行評審

7 引文 斯高帕斯(Scopus)

摘要

In this paper, a fast algorithm with its corresponding VLSI architecture is proposed to speed up the modular multiplication with a large modulus. By partitioning the operand (multiplier) into several equal-sized segments, and performing the multiplication and residue calculation of each segment in a pipelined fashion, a performance improvement can be achieved by using our algorithm compared with previous work. We also show an efficient procedure to accelerate the residue calculation and use carry-save addition to implement the architecture such that the critical path is independent of the size of the modulus. Therefore, the resulting architecture and implementation are very suitable to be applied to the high-speed RSA cryptosystem and can be easily implemented in VLSI technology.

原文English
頁(從 - 到)121-124
頁數4
期刊Proceedings - IEEE International Symposium on Circuits and Systems
2
出版狀態Published - 1998 一月 1
事件Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS. Part 5 (of 6) - Monterey, CA, USA
持續時間: 1998 五月 311998 六月 3

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

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