Pipelined VLSI with module structure design for discrete wavelet transforms

Ming Hwa Sheu, Shun Fa Cheng, Ming Der Shieh

研究成果: Conference article同行評審

4 引文 斯高帕斯(Scopus)

摘要

This paper presents an efficient pipelined VLSI architecture for computing the Discrete Wavelet Transform. The features of the architecture are 1) lower hardware cost, 2) shorter latency, 3) simplex control, 4) regular structure for VLSI implementation and 5) higher output throughput rate. Under considering the precision of the transformed data, the architecture has been done accuracy analysis to determine the appropriate bit-width for fitting the hardware executions. Finally, all components in the architecture are well designed and simulated based on the accuracy requirement.

原文English
頁(從 - 到)352-355
頁數4
期刊Proceedings - IEEE International Symposium on Circuits and Systems
4
出版狀態Published - 1996 一月 1
事件Proceedings of the 1996 IEEE International Symposium on Circuits and Systems, ISCAS. Part 1 (of 4) - Atlanta, GA, USA
持續時間: 1996 五月 121996 五月 15

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

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