Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base

Chun Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng Wen Wu

研究成果: Conference article同行評審

40 引文 斯高帕斯(Scopus)

摘要

Through-Silicon Vias (TSVs) enable high-density, low-latency, and low-power interconnects for system chips that consist of multiple dies. In "2.5D" Stacked ICs (2.5D-SICs), multiple dies without TSVs are stacked side-by-side on top of a passive silicon interposer base containing TSVs. In true 3D-SICs, multiple dies containing TSVs themselves are vertically stacked; one or multiple of such stacks are possibly placed on a passive silicon interposer. This paper proposes a post-bond test and design-for-test (DfT) strategy for 2.5D- and 3D-SICs containing a passive silicon interposer base. Functional interconnects in the interposer are reused as much as possible in order to keep the interposer cost low.

原文English
文章編號6139181
期刊Proceedings - International Test Conference
DOIs
出版狀態Published - 2011 十二月 1
事件International Test Conference 2011, ITC 2011 - Anaheim, CA, United States
持續時間: 2011 九月 182011 九月 23

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Applied Mathematics

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