Power consumption ameliorated for integrated gate driver circuit with low frequency clock

Chih Lung Lin, Chun Da Tu, Chia Che Hung, Mao Hsun Cheng, Chia En Wu, Yung Chih Chen

研究成果: Conference contribution

7 引文 斯高帕斯(Scopus)

摘要

This paper presents a novel low power consumption gate driver circuit with 12 TFTs and one capacitor which is made by hydrogenated amorphous silicon technology. The pull-down structure can not only prevent the floating of gate lines, but also suppress the threshold voltage shift of a-Si:H TFTs. According to the measurement results, the proposed gate driver circuit can be operated stably more than 10 days at high temperature (T = 100°C). Furthermore, the power consumption of the proposed gate driver circuit can be reduced 52.6% compared to the previously proposed gate driver circuit.

原文English
主出版物標題49th Annual SID Symposium, Seminar, and Exhibition 2011, Display Week 2011
頁面1285-1287
頁數3
出版狀態Published - 2011 十二月 1
事件49th Annual SID Symposium, Seminar, and Exhibition 2011, Display Week 2011 - Los Angeles, CA, United States
持續時間: 2011 五月 152011 五月 20

出版系列

名字49th Annual SID Symposium, Seminar, and Exhibition 2011, Display Week 2011
3

Other

Other49th Annual SID Symposium, Seminar, and Exhibition 2011, Display Week 2011
國家United States
城市Los Angeles, CA
期間11-05-1511-05-20

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

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