Power-effective ROM-less DDFS Design Approach with High SFDR Performance

Chua Chin Wang, Nanang Sulistiyanto, Hsiang Yu Shih, Yu Cheng Lin, Wei Wang

研究成果: Article同行評審

摘要

A ROM-less direct digital frequency synthesizer (DDFS) design approach based on interpolation schemes is proposed in this work. Besides achieving higher SFDR (spurious free dynamic range) and faster clock rate, detailed power estimation approach based on switching activity analysis of each logic sub-blocks is presented to explore the optimal solution. The parabolic equations with proper selection of coefficients and pipeline structure are utilized to enhance SFDR. A ROM-less DDFS using the proposed design approach is demonstrated by the physical implementation on Altera FPGA platform. The average SFDR is measured to be 68.4242 dBc with 1.1659 dBc deviation over 33 times of experiments. The measured SFDR is proved to outperform many previous DDFS works even if they were implemented on silicon.

原文English
頁(從 - 到)213-224
頁數12
期刊Journal of Signal Processing Systems
92
發行號2
DOIs
出版狀態Published - 2020 二月 1

All Science Journal Classification (ASJC) codes

  • 控制與系統工程
  • 理論電腦科學
  • 訊號處理
  • 資訊系統
  • 建模與模擬
  • 硬體和架構

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