Power-efficient and scalable load/store queue design via address compression

Yi Ying Tsai, Chia Jung Hsu, Chung-Ho Chen

研究成果: Conference contribution

1 引文 斯高帕斯(Scopus)

摘要

This paper proposes an address compression technique for load/store queue (LSQ) to improve the scalability and power efficiency. A load/store queue (LSQ) typically needs a fullyassociative CAM structure to search the address for collision and consequently poses scalability challenges of power consumption and area cost. Using the proposed approach, the LSQ can reduce the area cost ranging from 32% to 66% and power consumption ranging from 38% to 71%, depending on the compression parameter. The approach can provide 3.08% overall processor energy reduction and causes only 0.22% performance loss at an optimal configuration.

原文English
主出版物標題Proceedings of the 23rd Annual ACM Symposium on Applied Computing, SAC'08
頁面1523-1527
頁數5
DOIs
出版狀態Published - 2008 十二月 1
事件23rd Annual ACM Symposium on Applied Computing, SAC'08 - Fortaleza, Ceara, Brazil
持續時間: 2008 三月 162008 三月 20

出版系列

名字Proceedings of the ACM Symposium on Applied Computing

Other

Other23rd Annual ACM Symposium on Applied Computing, SAC'08
國家/地區Brazil
城市Fortaleza, Ceara
期間08-03-1608-03-20

All Science Journal Classification (ASJC) codes

  • 軟體

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