Power-efficient decoder implementation based on state transparent convolutional codes

Y. H. Shiau, H. Y. Yang, Pei-Yin Chen, S. G. Huang

研究成果: Article同行評審

7 引文 斯高帕斯(Scopus)

摘要

In this study, a power-efficient very large-scale integration (VLSI) implementation for the convolutional code decoder is presented. Based on the state transparent convolutional code definition, the receiving codewords are classified into non-erroneous and erroneous segments separately. Different from the conventional Viterbi decoder (VD), the authors use a low-complexity decoder, denoted as bit reverse decoder, to recover the non-erroneous segments using reverse operation with a little power consumption and present the segment-based VD to decode the erroneous codeword segments. Then, the clock-gating technique is employed to switch between segment-based VD and bit reverse decoder for power saving. To further reduce the power consumption, the authors group registers into several segments in the survivor memory unit of the segment-based VD and also apply clock gating to each segment individually. According to the number of consecutive erroneous codeword segments, the corresponding numbers of register segments in the survivor memory unit are enabled and other register segments are clock-gated to reduce the switching activities. Besides, our design determines the start and terminal states of the survivor path to obtain correct results of erroneous segments without bit-error rate degradation. As compared with other decoders, our design requires less power without decreasing the decoding performance.

原文English
頁(從 - 到)227-234
頁數8
期刊IET Circuits, Devices and Systems
6
發行號4
DOIs
出版狀態Published - 2012 七月 1

All Science Journal Classification (ASJC) codes

  • 控制與系統工程
  • 電氣與電子工程

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