During IC packaging processes, some defects such as wire sweep, paddle shift and warpage etc, may happen. One critical issue for IC packaging is the warpage induced during molding process. This issue is even more serious for large and thin packages. Previous research works have focused on the stresses or warpage analyses with different coefficient of thermal expansion (CTE) between constituent materials and neglected the cure shrinkage effects. However, more and more studies indicate that the calculation of residual stresses or warpage due to CTE difference only is not accurate enough. It would be necessary to consider all of the thermal, cure reaction and resin compressibility effects at the same time in order to better predict warpage of IC packages after molding. The cure reaction and compressibility properties of EMC can be described by a function of pressure, volume, temperature and degree of cure. The relation is called the P-V-T-C equation   . This paper adopted the P-V-T-C and CTE difference approach to simulate the process induced warpage. Due to practical requirements, the Taguchi method was employed to find the close to optimum processing parameters. The effects of several important processing parameters such as transfer pressure, packing pressure, mold temperature and curing time on the amount of warpage in packages during molding were studied in this paper. In this study, a thin small outline package (TSOP) DBS-27P, was used for the simulation. The simulation results were verified with experiments. It showed that the approach of considering both thermal and cure/compressibility effects could better predict the amount of warpage for TSOP package. It was also found that the Taguchi method was useful to assist in obtaining the close to optimum processing parameters with respect to the amount of warpage.