Process and Simulation design of Silicon-On-Insulator (SOI) NMOS

Zih Fei Chen, Yu Sheng Lai, Cheng Ming Huang, Yeong Her Wang, Meng Hsueh Chiang

研究成果: Conference contribution

1 引文 斯高帕斯(Scopus)

摘要

As CMOS devices continue to shrink, traditional bulk-based MOSFETs are facing physical limits. In addition, the process compatibility of SOI and bulk has been confirmed. We develop an SOI-based NMOS technology to evaluate the scalability and use the Technology Computer Aided Design (TCAD) simulation software for verification. We find that the threshold voltage (Vth) of the SOI NMOS samples is over 0.5 V. In this paper, we introduce the SOI technology and discuss the calibration of Vth in process simulation by doping phosphorus close to the oxide layer on the channel. First, we simulate the annealing rate to optimize the device characteristics, and then adjust the Vth with the channel doping of phosphorus. The simulation results show that before the gate oxide layer is deposited, doping with appropriate phosphorus concentration and implantation energy can effectively control Vth at 0.3 V, and achieve optimized subthreshold swing and maintain high Ion/Ioff ratio at the same time, which can be applied to low-power ICs.

原文English
主出版物標題2023 IEEE Nanotechnology Materials and Devices Conference, NMDC 2023
發行者Institute of Electrical and Electronics Engineers Inc.
頁面313-317
頁數5
ISBN(電子)9798350335460
DOIs
出版狀態Published - 2023
事件18th IEEE Nanotechnology Materials and Devices Conference, NMDC 2023 - Paestum, Italy
持續時間: 2023 10月 222023 10月 25

出版系列

名字2023 IEEE Nanotechnology Materials and Devices Conference, NMDC 2023

Conference

Conference18th IEEE Nanotechnology Materials and Devices Conference, NMDC 2023
國家/地區Italy
城市Paestum
期間23-10-2223-10-25

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程
  • 材料化學
  • 電子、光磁材料
  • 儀器
  • 材料科學(雜項)

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