TY - GEN
T1 - Process and Simulation design of Silicon-On-Insulator (SOI) NMOS
AU - Chen, Zih Fei
AU - Lai, Yu Sheng
AU - Huang, Cheng Ming
AU - Wang, Yeong Her
AU - Chiang, Meng Hsueh
N1 - Publisher Copyright:
© 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - As CMOS devices continue to shrink, traditional bulk-based MOSFETs are facing physical limits. In addition, the process compatibility of SOI and bulk has been confirmed. We develop an SOI-based NMOS technology to evaluate the scalability and use the Technology Computer Aided Design (TCAD) simulation software for verification. We find that the threshold voltage (Vth) of the SOI NMOS samples is over 0.5 V. In this paper, we introduce the SOI technology and discuss the calibration of Vth in process simulation by doping phosphorus close to the oxide layer on the channel. First, we simulate the annealing rate to optimize the device characteristics, and then adjust the Vth with the channel doping of phosphorus. The simulation results show that before the gate oxide layer is deposited, doping with appropriate phosphorus concentration and implantation energy can effectively control Vth at 0.3 V, and achieve optimized subthreshold swing and maintain high Ion/Ioff ratio at the same time, which can be applied to low-power ICs.
AB - As CMOS devices continue to shrink, traditional bulk-based MOSFETs are facing physical limits. In addition, the process compatibility of SOI and bulk has been confirmed. We develop an SOI-based NMOS technology to evaluate the scalability and use the Technology Computer Aided Design (TCAD) simulation software for verification. We find that the threshold voltage (Vth) of the SOI NMOS samples is over 0.5 V. In this paper, we introduce the SOI technology and discuss the calibration of Vth in process simulation by doping phosphorus close to the oxide layer on the channel. First, we simulate the annealing rate to optimize the device characteristics, and then adjust the Vth with the channel doping of phosphorus. The simulation results show that before the gate oxide layer is deposited, doping with appropriate phosphorus concentration and implantation energy can effectively control Vth at 0.3 V, and achieve optimized subthreshold swing and maintain high Ion/Ioff ratio at the same time, which can be applied to low-power ICs.
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U2 - 10.1109/NMDC57951.2023.10344290
DO - 10.1109/NMDC57951.2023.10344290
M3 - Conference contribution
AN - SCOPUS:85182025320
T3 - 2023 IEEE Nanotechnology Materials and Devices Conference, NMDC 2023
SP - 313
EP - 317
BT - 2023 IEEE Nanotechnology Materials and Devices Conference, NMDC 2023
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 18th IEEE Nanotechnology Materials and Devices Conference, NMDC 2023
Y2 - 22 October 2023 through 25 October 2023
ER -