Processor-programmable memory BIST for bus-connected embedded memories

Ching Hong Tsai, Cheng Wen Wu

研究成果: Conference contribution

26 引文 斯高帕斯(Scopus)

摘要

We present a processor-programmable built-in self-test (BIST) scheme suitable for embedded memory testing in the system-on-a-chip (SOC) environment. The proposed BIST circuit can be programmed via an on chip microprocessor. Upon receiving the commands from the microprocessor, the BIST circuit generates pre-defined test patterns and compares the memory outputs with the expected outputs. Most popular memory test algorithms can be realized by properly programming the BIST circuit using the processor instructions. Compared with processor-based memory BIST schemes that use an assembly-language program to generate test patterns and compare the memory outputs, the test time of the proposed memory BIST scheme is greatly reduced.

原文English
主出版物標題Proceedings of the ASP-DAC 2001
主出版物子標題Asia and South Pacific Design Automation Conference 2001
發行者Institute of Electrical and Electronics Engineers Inc.
頁面325-330
頁數6
ISBN(電子)0780366336
DOIs
出版狀態Published - 2001 1月 1
事件Asia and South Pacific Design Automation Conference 2001, ASP-DAC 2001 - Yokohama, Japan
持續時間: 2001 1月 302001 2月 2

出版系列

名字Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
2001-January

Other

OtherAsia and South Pacific Design Automation Conference 2001, ASP-DAC 2001
國家/地區Japan
城市Yokohama
期間01-01-3001-02-02

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程
  • 電腦科學應用
  • 電腦繪圖與電腦輔助設計

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