Programmable pacing channel with a fully on-chip LDO regulator for cardiac pacemaker

Chih Jen Cheng, Chung Jui Wu, Shuenn-Yuh Lee

研究成果: Conference contribution

16 引文 斯高帕斯(Scopus)

摘要

A novel dual-voltage pacing system for implant pacemaker is presented in this paper. In order to reduce supply voltage ripple and diminish process variation imposed on the divided-resistor, a fully on-chip low-dropout (LDO) regulator is proposed. Meanwhile, the adjustable pacing circuit together with a sense feedback is employed to deliver electrical stimuli of 16-step amplitudes to induce cardiac contraction. The pacing circuit with a LDO regulator was fabricated in TSMC 0.35-μm CMOS technology, consuming total power of 1.29 μW including 185 nA of ground current in 1.2-V LDO and having a power consumption of 30 nW in the 1-V pacing step controller. Experimental results demonstrate that the proposed LDO regulator features a powersupply rejection ratio (PSRR) of -30 dB with the output ripple of 570 μVpp under the input sinusoidal wave of 19.6 mVpp. Even with the load current up to 10 μA, LDO yields a line regulation that is less than 3% deviation.

原文English
主出版物標題Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
頁面285-288
頁數4
DOIs
出版狀態Published - 2008 12月 1
事件2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008 - Fukuoka, Japan
持續時間: 2008 11月 32008 11月 5

出版系列

名字Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008

Other

Other2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
國家/地區Japan
城市Fukuoka
期間08-11-0308-11-05

All Science Journal Classification (ASJC) codes

  • 硬體和架構
  • 電氣與電子工程

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