Programmable reference for power-aware DVS

Chun Hung Yang, Jiunn Hung Shiau, Chien Hung Tsai

研究成果: Conference contribution

1 引文 斯高帕斯(Scopus)

摘要

This paper present an efficient technique and mixed-level design of programmable generating accurate reference voltage. The technique comprises a second-order error feedback Σ-Δ modulators sequence, which is then smoothed by a second-order RC filter. An FPGA-based test platform for the to-bit programmable reference is implemented for hardware realization to verify the proposed design approach. Experimental results show that the linear range of voltage is obtained from 0.4 to 3V and the step response between 0.9 and 1.2 V is equal to 1.5 μs, thus validating the functionality of the mixed-level model. Further verification is found by the experimental results being equivalent to the simulation results.

原文English
主出版物標題2010 2nd International Symposium on Aware Computing, ISAC 2010 - Symposium Guide
頁面166-170
頁數5
DOIs
出版狀態Published - 2010 十二月 1
事件2010 2nd International Symposium on Aware Computing, ISAC 2010 - Sapporo, Japan
持續時間: 2010 十一月 12010 十一月 4

出版系列

名字2010 2nd International Symposium on Aware Computing, ISAC 2010 - Symposium Guide

Other

Other2010 2nd International Symposium on Aware Computing, ISAC 2010
國家Japan
城市Sapporo
期間10-11-0110-11-04

All Science Journal Classification (ASJC) codes

  • Computational Theory and Mathematics
  • Computer Science Applications

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