Programmable reference for power-aware DVS

Chun Hung Yang; Jiunn Hung Shiau; Chien Hung Tsai

doi:10.1109/ISAC.2010.5670473

Programmable reference for power-aware DVS

Chun Hung Yang, Jiunn Hung Shiau, Chien Hung Tsai

電機工程學系

研究成果: Conference contribution

1 引文斯高帕斯（Scopus）

摘要

This paper present an efficient technique and mixed-level design of programmable generating accurate reference voltage. The technique comprises a second-order error feedback Σ-Δ modulators sequence, which is then smoothed by a second-order RC filter. An FPGA-based test platform for the to-bit programmable reference is implemented for hardware realization to verify the proposed design approach. Experimental results show that the linear range of voltage is obtained from 0.4 to 3V and the step response between 0.9 and 1.2 V is equal to 1.5 μs, thus validating the functionality of the mixed-level model. Further verification is found by the experimental results being equivalent to the simulation results.

原文	English
主出版物標題	2010 2nd International Symposium on Aware Computing, ISAC 2010 - Symposium Guide
頁面	166-170
頁數	5
DOIs	https://doi.org/10.1109/ISAC.2010.5670473
出版狀態	Published - 2010 十二月 1
事件	2010 2nd International Symposium on Aware Computing, ISAC 2010 - Sapporo, Japan 持續時間: 2010 十一月 1 → 2010 十一月 4

出版系列

名字	2010 2nd International Symposium on Aware Computing, ISAC 2010 - Symposium Guide

Other

Other	2010 2nd International Symposium on Aware Computing, ISAC 2010
國家	Japan
城市	Sapporo
期間	10-11-01 → 10-11-04

All Science Journal Classification (ASJC) codes

Computational Theory and Mathematics
Computer Science Applications

存取文件

10.1109/ISAC.2010.5670473

其它文件與鏈接

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引用此

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abstract = "This paper present an efficient technique and mixed-level design of programmable generating accurate reference voltage. The technique comprises a second-order error feedback Σ-Δ modulators sequence, which is then smoothed by a second-order RC filter. An FPGA-based test platform for the to-bit programmable reference is implemented for hardware realization to verify the proposed design approach. Experimental results show that the linear range of voltage is obtained from 0.4 to 3V and the step response between 0.9 and 1.2 V is equal to 1.5 μs, thus validating the functionality of the mixed-level model. Further verification is found by the experimental results being equivalent to the simulation results.",

author = "Yang, {Chun Hung} and Shiau, {Jiunn Hung} and Tsai, {Chien Hung}",

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Yang, CH, Shiau, JH & Tsai, CH 2010, Programmable reference for power-aware DVS. 於 2010 2nd International Symposium on Aware Computing, ISAC 2010 - Symposium Guide., 5670473, 2010 2nd International Symposium on Aware Computing, ISAC 2010 - Symposium Guide, 頁 166-170, 2010 2nd International Symposium on Aware Computing, ISAC 2010, Sapporo, Japan, 10-11-01. https://doi.org/10.1109/ISAC.2010.5670473

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N2 - This paper present an efficient technique and mixed-level design of programmable generating accurate reference voltage. The technique comprises a second-order error feedback Σ-Δ modulators sequence, which is then smoothed by a second-order RC filter. An FPGA-based test platform for the to-bit programmable reference is implemented for hardware realization to verify the proposed design approach. Experimental results show that the linear range of voltage is obtained from 0.4 to 3V and the step response between 0.9 and 1.2 V is equal to 1.5 μs, thus validating the functionality of the mixed-level model. Further verification is found by the experimental results being equivalent to the simulation results.

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