Programmable reference for power-aware DVS

This paper present an efficient technique and mixed-level design of programmable generating accurate reference voltage. The technique comprises a second-order error feedback Σ-Δ modulators sequence, which is then smoothed by a second-order RC filter. An FPGA-based test platform for the to-bit programmable reference is implemented for hardware realization to verify the proposed design approach. Experimental results show that the linear range of voltage is obtained from 0.4 to 3V and the step response between 0.9 and 1.2 V is equal to 1.5 μs, thus validating the functionality of the mixed-level model. Further verification is found by the experimental results being equivalent to the simulation results.