Programmable system-on-chip for silicon prototyping

Chun Ming Huang, Chien Ming Wu, Chih Chyau Yang, Shih Lun Chen, Chi Shi Chen, Jiann Jenn Wang, Kuen Jong Lee, Chin Long Wey

研究成果: Article同行評審

14 引文 斯高帕斯(Scopus)

摘要

This paper presents a programmable system-on-chip (SoC) design methodology which integrates multiple heterogeneous SoC design projects into a single chip such that the total silicon prototyping cost for these projects can be greatly reduced by sharing a common SoC platform. In this implementation, an integrated SoC platform is comprised of eight SoC projects. When these eight SoC projects are designed separately, the total area is approximately 143.03 mm2, while the area of the integrated platform is about 24.43 mm2. The area reduction is significant, so is the fabrication cost. Once the integrated platform chip is fabricated, three programming schemes are carried out to allow the integrated chip to act as the individual SoC design projects. A test chip is designed and implemented using the TSMC 0.13-μm CMOS generic logic process technology.

原文English
文章編號4926187
頁(從 - 到)830-838
頁數9
期刊IEEE Transactions on Industrial Electronics
58
發行號3
DOIs
出版狀態Published - 2011 三月 1

All Science Journal Classification (ASJC) codes

  • Control and Systems Engineering
  • Electrical and Electronic Engineering

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