Programmable System-on-chip (SoC) for silicon prototyping

Chun Ming Huang, Chien Ming Wu, Chih Chyau Yang, Kuen Jong Lee, Chin Long Wey

研究成果: Conference contribution

8 引文 斯高帕斯(Scopus)

摘要

This paper presents a Programmable SoC (Systemon-chip) design methodology which integrates multiple heterogeneous SoC design projects into a single chip such that the total silicon prototyping cost for these projects can be greatly reduced by sharing the common SoC platform. Results show that an integrated SoC platform is comprised of eight SoC projects. When these eight SoC projects are designed separately, the total area is approximately 143.03mm2, while the area of the integrated platform is about 24.43mm2. The area reduction is significant, so is the fabrication cost. Once the integrated platform chip is fabricated, three programming schemes are carried out to allow the integrated chip to act as the individual SoC design projects. A test chip is designed and implemented using the TSMC 0.13um CMOS generic logic process technology. The development of second generation MP-SoC chip is also outlined in this paper.

原文English
主出版物標題2008 IEEE International Symposium on Industrial Electronics, ISIE 2008
頁面1976-1981
頁數6
DOIs
出版狀態Published - 2008 12月 29
事件2008 IEEE International Symposium on Industrial Electronics, ISIE 2008 - Cambridge, United Kingdom
持續時間: 2008 6月 302008 7月 2

出版系列

名字IEEE International Symposium on Industrial Electronics

Other

Other2008 IEEE International Symposium on Industrial Electronics, ISIE 2008
國家/地區United Kingdom
城市Cambridge
期間08-06-3008-07-02

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程
  • 控制與系統工程

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