Proteus system architecture and organization

Aran K. Somani, Craig Wittenbrink, Robert M. Haralick, Linda G. Shapiro, Jenq Neng Hwang, Chung Ho Chen, Robert Johnson, Kenneth Cooper

研究成果: Conference contribution

9 引文 斯高帕斯(Scopus)


The Proteus architecture is a highly parallel MIMD, multiple instruction multiple data, machine, optimized for large granularity tasks such as machine vision and image processing. The system can achieve 20 G-flops (80 G-flops peak). It accepts data via multiple serial links at a rate of up to 640 megabytes/second. The system employs hierarchical reconfigurable interconnection network with the highest level being a circuit switched Enhanced Hypercube serial interconnection network for internal data transfers. The system is designed to use 256 to 1,024 RISC processors. The processors use 1 M byte external Read/Write Allocating Caches for reduced multiprocessor contention. The system detects, locates and replaces faulty subsystems using redundant hardware to facilitate fault tolerance. The parallelism is directly controllable through an advanced software system for partitioning, scheduling and development.

主出版物標題Proceedings - 5th International Parallel Processing Symposium, IPPS 1991
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)0818691670, 9780818691676
出版狀態Published - 1991 一月 1
事件5th International Parallel Processing Symposium, IPPS 1991 - Anaheim, United States
持續時間: 1991 四月 301991 五月 2


名字Proceedings - 5th International Parallel Processing Symposium, IPPS 1991


Conference5th International Parallel Processing Symposium, IPPS 1991
國家/地區United States

All Science Journal Classification (ASJC) codes

  • 計算數學
  • 硬體和架構
  • 人工智慧
  • 電腦網路與通信
  • 電腦科學應用


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