P3A: A partitionable parallel/pipeline architecture for real-time image processing

C. Thomas Gray, Wentai Liu, Thomas Hughes, Ralph Cavin, Sh shing Chen

研究成果: Conference article同行評審

2 引文 斯高帕斯(Scopus)

摘要

A high-performance partitionable parallel/pipeline architecture (P3A) that is capable of real-time image processing is discussed. The architecture consists of P disjoint pipes of L processors each, connected together through a novel wraparound memory. Many different problem classes, including shuffle-exchange, butterfly, and tree algorithms, can be easily mapped into P3A. The power of the architecture lies in its ability to exploit both the spatial and temporal aspects of concurrency balancing parallelism and pipelining.

原文English
頁(從 - 到)529-531
頁數3
期刊Proceedings - International Conference on Pattern Recognition
2
出版狀態Published - 1990
事件Proceedings of the 10th International Conference on Pattern Recognition - Atlantic City, NJ, USA
持續時間: 1990 6月 161990 6月 21

All Science Journal Classification (ASJC) codes

  • 電腦視覺和模式識別

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