PVD TiN metal gate MOSFETs on bulk silicon and fully depleted silicon-on-insulator (FDSOI) substrates for deep sub-quarter micron CMOS technology

B. Maiti, P. J. Tobin, C. Hobbs, R. I. Hegde, F. Huang, D. L. O'Meara, D. Jovanovic, M. Mendicino, J. Chen, D. Connelly, O. Adetutu, J. Mogab, J. Candelaria, L. B. La

研究成果: Conference article同行評審

40 引文 斯高帕斯(Scopus)

摘要

We report here for the first time an evaluation of a polysilicon capped physical vapor deposited (PVD) titanium nitride (TiN) metal gate integration on sub-quarter micron CMOSFETs using bulk Si and FDSOI substrates. In addition to eliminating poly depletion effects and lowering gate line resistance, the use of TiN gate enables lower Vt when used with FDSOI substrates instead of bulk Si. Excellent on-off and short channel characteristics can be obtained with TiN gate. Issues associated with Leff and reliability are also discussed.

原文English
頁(從 - 到)781-784
頁數4
期刊Technical Digest - International Electron Devices Meeting
出版狀態Published - 1998 十二月 1
事件Proceedings of the 1998 IEEE International Electron Devices Meeting - San Francisco, CA, USA
持續時間: 1998 十二月 61998 十二月 9

All Science Journal Classification (ASJC) codes

  • 電子、光磁材料
  • 凝聚態物理學
  • 電氣與電子工程
  • 材料化學

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