Raisin: Redundancy analysis algorithm simulation

Rei Fu Huang, Jin Fu Li, Jen Chieh Yeh, Cheng Wen Wu

研究成果: Article同行評審

26 引文 斯高帕斯(Scopus)

摘要

Embedded memories are among the most widely used cores in current SoC designs. Memory cores usually dominate the area and yield of the system chip, requiring repair methodologies to make a profitable product. To increase the efficiency of redundancy repair, and thus final yield, the authors propose Raisin (Redundancy Analysis Algorithm Simulation). The Raisin tool calculates the repair rate and yield (after repair) of the given redundancy analysis (RA) algorithm and the associated memory configuration and redundancy structure. With Raisin, users can easily assess and plan redundant (spare) elements, and subsequently develop the built-in redundancy analysis (BIRA) algorithms and circuits that are essential to built-in self-repair of embedded memories. To make the verification of the BISR design easier, Raisin also generates its testbench. Another important feature is that given a RAM test algorithm, Raisin simulates the real sequence of the faults detected, improving the accuracy of the analysis results. Experimental results show that Raisin can improve repair rates in redundancy structures by as much as 10% without increasing area overhead. Raisin has been used in industry cases, including embedded SRAM and flash memory circuits.

原文English
頁(從 - 到)386-396
頁數11
期刊IEEE Design and Test of Computers
24
發行號4
DOIs
出版狀態Published - 2007 十二月 1

All Science Journal Classification (ASJC) codes

  • 軟體
  • 硬體和架構
  • 電氣與電子工程

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