RAMSES: A fast memory fault simulator

Chi Feng Wu, Chih Tsun Huang, Cheng Wen Wu

研究成果: Conference contribution

摘要

In this paper, we present a memory fault simulator called the Random Access Memory Simulator for Error Screening (RAMSES). Although it was designed based on some well-known memory fault models, the algorithm that we developed ensures that new fault models can be included easily by adding new fault descriptors instead of modifying the algorithm or program. With RAMSES, the time complexity of memory fault simulation is improved from O(N3) to O(N2), where N is the memory capacity in terns of bits. Our approach requires only a small amount of extra memory space. Simulation results by RAMSES show that running the proposed cocktail-March tests can significantly reduce the test time. With the help of RAMSES, an efficient test algorithm called March-CW was developed for word-oriented memories.

原文English
主出版物標題Proceedings - 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999
發行者Institute of Electrical and Electronics Engineers Inc.
頁面165-173
頁數9
ISBN(電子)076950325X, 9780769503257
DOIs
出版狀態Published - 1999 一月 1
事件1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999 - Albuquerque, United States
持續時間: 1999 十一月 11999 十一月 3

出版系列

名字Proceedings - 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999

Conference

Conference1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999
國家United States
城市Albuquerque
期間99-11-0199-11-03

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

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  • 引用此

    Wu, C. F., Huang, C. T., & Wu, C. W. (1999). RAMSES: A fast memory fault simulator. 於 Proceedings - 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999 (頁 165-173). [802882] (Proceedings - 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DFTVS.1999.802882