Reconfigurable architecture for entropy decoding and inverse transform in H.264

Chia Cheng Lo, Shang Ta Tsai, Ming Der Shieh

研究成果: Article同行評審

10 引文 斯高帕斯(Scopus)


Reconfigurable hardware is an effective design option for dealing with the increasing demands of flexibility and computation power in system design. This paper explores techniques to combine the two entropy decoding methods defined in the H.264 standard, context-based adaptive binary arithmetic coding (CABAC) and context-based adaptive variable length coding (CAVLC), using a coarse-grain reconfigurable architecture. An analyzing of the similarities and differences between these two decoding processes shows that CAVLC can be effectively merged into a CABAC decoder. Experimental results show that about 1.5K gates can be saved using the proposed reconfigurable cell (RC) architecture, which corresponds to a 25.4% area savings in the implementation of the CAVLC decoder. Using the idle time in RC arrays, the base cell can be extended to carry out the inverse transform with very limited overhead. The proposed entropy decoder design, which operates at 66 MHz, can decode video sequences at Baseline and Main profiles at Level 3.0 under the real-time constraint.

頁(從 - 到)1670-1676
期刊IEEE Transactions on Consumer Electronics
出版狀態Published - 2010 8月

All Science Journal Classification (ASJC) codes

  • 媒體技術
  • 電氣與電子工程


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