Reconfigurable homogenous multi-core FFT processor architectures for hybrid SISO/MIMO OFDM wireless communications

Chin Long Wey, Shin Yo Lin, Pei Yun Tsai, Ming Der Shieh

研究成果: Article同行評審

1 引文 斯高帕斯(Scopus)

摘要

Multi-core processors have been attracting a great deal of attention. In the domain of signal processing for communications, the current trends toward rapidly evolving standards and formats, and toward algorithms adaptive to dynamic factors in the environment, require programmable solutions that possess both algorithm flexibility and low implementation complexity. Reconfigurable architectures have demonstrated better tradeoffs between algorithm flexibility, implementation complexity, and energy efficiency. This paper presents a reconfigurable homogeneous memory-based FFT processor (MBFFT) architecture integrated in a single chip to provide hybrid SISO/MIMO OFDM wireless communication systems. For example, a reconfigurable MBFFT processor with eight processing elements (PEs) can be configured for one DVB-T/H with N=8192 and two 802.11n with N=128. The reconfigurable processors can perfectly fit the applications of Software Defined Radio (SDR) which requires more hardware flexibility.

原文English
頁(從 - 到)1530-1539
頁數10
期刊IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E94-A
發行號7
DOIs
出版狀態Published - 2011 七月

All Science Journal Classification (ASJC) codes

  • 訊號處理
  • 電腦繪圖與電腦輔助設計
  • 電氣與電子工程
  • 應用數學

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