Reconfigurable Parser Architecture Design with Microprogrammed Controller for Multiple Purposes

Gwo Giun (Chris) Lee, Chun Fu (Richard) Chen, Ching Jui Hsiao

研究成果: Article同行評審

1 引文 斯高帕斯(Scopus)


This paper utilizes the flexibility of microprogrammed controller with reloadable microcodes for developing reconfigurable parser for multiple purposes. Based on control-dataflow, with microprogrammed controller taken into consideration due to the nature of feedback control in parser, this paper proposes a reconfigurable parser through extracting control commonalities to form shared microinstructions so that the current architecture alleviates the cost in switching control signals for distinct purposes. We employ reconfigurable video coding as a case study to justify the advantages in reconfigurable parser with microprogrammed controller in comparison with finite state machine based controller. Using TSMC 0.18 μm CMOS technology at 108 MHz operating frequency, we reduce 8.93 % gate counts and increase throughput rate twice in comparison with individually implemented finite state machine based controller. We have demonstrated that microprogrammed controller is the trend of flexible architecture design for multiple purposes. Owing to high proportion of shared microinstruction, the higher saving ratio could be envision when multiple purposes are involved in the proposed reconfigurable parser, e.g., more video coding standards.

頁(從 - 到)67-81
期刊Journal of Signal Processing Systems
出版狀態Published - 2017 7月 1

All Science Journal Classification (ASJC) codes

  • 控制與系統工程
  • 理論電腦科學
  • 訊號處理
  • 資訊系統
  • 建模與模擬
  • 硬體和架構


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