Reduction of power consumption in scan-based circuits during test application by an input control technique

T. C. Huang, K. J. Lee

研究成果: Article同行評審

43 引文 斯高帕斯(Scopus)

摘要

This paper proposes a novel technique to minimize the switching activity of full-scan circuits during test application time. The basic idea is to identify an input control pattern (CP) for a full-scan circuit such that by applying the pattern to the primary inputs of the circuit during the scan operation, the switching activity in the combinational part can be reduced or even eliminated. A D-algorithm-like CP generator is developed to generate the CP. This input control technique can be utilized together with the existing vector ordering or latch ordering techniques. Experimental results show that the vector ordering and the latch ordering techniques can achieve 22.37% of average improvement by redoing the experiments in previous work using our test sets, while 34.23% average improvement can be achieved if the input control technique is employed after the latch ordering and vector ordering techniques.

原文English
頁(從 - 到)911-917
頁數7
期刊IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
20
發行號7
DOIs
出版狀態Published - 2001 七月

All Science Journal Classification (ASJC) codes

  • 軟體
  • 電腦繪圖與電腦輔助設計
  • 電氣與電子工程

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