This paper introduces a routability-driven macro placement algorithm for mixed-size circuits and pays special attention to the effect of regular placement of macros. Once macros are placed with regularity, powerplanning will become easier and better routability can be obtained. Our methodology consists of two stages. First, placement prototyping stage distributes cells and macros over a placement region while keeping those macros and cells with a strong connection and in similar hierarchies tied together. This is facilitated by clustering macros and cells properly in advance. In the second stage, a deterministic macro legalization algorithm is proposed to arrange macros without deteriorating the result obtained in the previous stage. Although several macro legalization algorithms have been proposed in recent years, most of these works adopt the simulated annealing algorithm which usually takes longer runtime. Moreover, they either cannot handle preplaced macros or require preplaced macros to be abutted to chip boundaries. Unlike these approaches, our method iteratively places a macro by extracting available space for it. Experimental results demonstrate the efficiency and effectiveness of our method according to real industry circuits.
|頁（從 - 到）||57-68|
|期刊||IEEE Transactions on Very Large Scale Integration (VLSI) Systems|
|出版狀態||Published - 2019 一月|
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering