The performance of Hebbian-type associative memories (HAMs) in the presence of faulty interconnections is examined, and equations for predicting network reliability are developed. Optical and VLSI implementations of HAMs are introduced, and the distributions of faulty interconnections in both implementations are discussed. The interconnection faults considered are the equivalent of open-circuit and short-circuit synaptic interconnections. Equations relating the probability of direct one-step convergence (Pdc) to the percentage of failed interconnections are developed for both types of interconnection faults. Monte Carlo simulations indicate that the equations considered here can estimate Pdc accurately. Based on the equations, network performance with failed interconnections can be predicted and trade-offs in network design can be determined before proceeding to implementation. The performance of networks with clustered failed interconnections is also discussed and compared with that of networks with randomly distributed faults. The present results are discussed from the implementation point of view.