Routability-driven tsv-Aware floorplanning methodology for fixed-outline 3-d ics

Jai Ming Lin, Jung An Yang

研究成果: Article同行評審

3 引文 斯高帕斯(Scopus)

摘要

Although 3-D floorplanning has been studied widely, routability which is a very important issue in modern integrated circuit (IC) designs is rarely discussed. Floorplanning in 3-D ICs is much difficult than that in 2-D ICs because of large difference in sizes between modules and through silicon vias (TSVs), which are key components in 3-D ICs. And the locations of TSVs have great impact on wirelength and routability in resulting floorplans. Hence, this paper proposes a TSV-Aware 3-D floorplanning methodology which can consider wirelength and routability at the same time under the fixed-outline constraint. Unlike most of previous works which completely apply the simulated annealing algorithm, our methodology mainly apply deterministic algorithms to resolve the problem. Thus, our approach is more efficient and flexible than previous works. Experimental results have demonstrated that the proposed methodology can significantly reduce routing congestion in 3-D ICs with a slight increase in wirelength.

原文English
文章編號7904617
頁(從 - 到)1856-1868
頁數13
期刊IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
36
發行號11
DOIs
出版狀態Published - 2017 十一月

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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