跳至主導覽 跳至搜尋 跳過主要內容

Scalable montgomery modular multiplication architecture with low-latency and low-memory bandwidth requirement

研究成果: Article同行評審

20   連結會在新分頁中開啟 引文 斯高帕斯(Scopus)

摘要

Montgomery modular multiplication is widely used in public-key cryptosystems. This work shows how to relax the data dependency in conventional word-based algorithms to maximize the possibility of reusing the current words of variables. With the greatly relaxed data dependency, we then proposed a novel scheduling scheme to alleviate the number of memory access in the developed scalable architecture. Analytical results show that the memory bandwidth requirement of the proposed scalable architecture is almost (1/(w-1)) times that of conventional scalable architectures, where (w) denotes word size. The proposed one also retains a latency of exactly one cycle between the operations of the same words in two consecutive iterations of the Montgomery modular multiplication algorithm when employing enough processing elements. Compared to the design in the related work, experimental results demonstrate that the proposed one achieves an almost 54 percent reduction in power consumption with no degradation in throughput. The reduced number of memory access not only leads to lower power consumption, but also facilitates the design of scalable architectures for any precision of operands.

原文English
文章編號6296657
頁(從 - 到)475-483
頁數9
期刊IEEE Transactions on Computers
63
發行號2
DOIs
出版狀態Published - 2014 2月

All Science Journal Classification (ASJC) codes

  • 軟體
  • 理論電腦科學
  • 硬體和架構
  • 計算機理論與數學

指紋

深入研究「Scalable montgomery modular multiplication architecture with low-latency and low-memory bandwidth requirement」主題。共同形成了獨特的指紋。

引用此