TY - GEN
T1 - Scalable security processor design and its implementation
AU - Wang, Chen Hsing
AU - Yeh, Jen Chieh
AU - Huang, Chih Tsun
AU - Wu, Cheng Wen
PY - 2006/12/1
Y1 - 2006/12/1
N2 - This paper presents a security processor to accelerate cryptographic processing in modern security applications. Our security processor is capable of popular cryptographic functions such as RSA, AES, hashing and random number generation, etc. With proposed Crypto-DMA controller, data gathering and scattering become flexible for security processing, using a simple descriptor-based programming model. The architecture of the security processor with its core-based platform is scalable and configurable for security variations in performance, cost and power consumption. Different number of data channels and crypto-engines can be used to meet the specifications. In addition, a DFT (design for test) platform is also implemented for the design-test integration. The security processor has been fabricated (using UMC 0.18μm CMOS technology) and measured. The core area is 3.899mm × 2.296mm (525K gates approximately) and the operating clock rate is 66MHz.
AB - This paper presents a security processor to accelerate cryptographic processing in modern security applications. Our security processor is capable of popular cryptographic functions such as RSA, AES, hashing and random number generation, etc. With proposed Crypto-DMA controller, data gathering and scattering become flexible for security processing, using a simple descriptor-based programming model. The architecture of the security processor with its core-based platform is scalable and configurable for security variations in performance, cost and power consumption. Different number of data channels and crypto-engines can be used to meet the specifications. In addition, a DFT (design for test) platform is also implemented for the design-test integration. The security processor has been fabricated (using UMC 0.18μm CMOS technology) and measured. The core area is 3.899mm × 2.296mm (525K gates approximately) and the operating clock rate is 66MHz.
UR - http://www.scopus.com/inward/record.url?scp=34250782103&partnerID=8YFLogxK
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U2 - 10.1109/ASSCC.2005.251790
DO - 10.1109/ASSCC.2005.251790
M3 - Conference contribution
SN - 0780391624
SN - 9780780391628
T3 - 2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005
SP - 513
EP - 516
BT - 2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005
PB - IEEE Computer Society
T2 - 1st IEEE Asian Solid-State Circuits Conference, ASSCC 2005
Y2 - 1 November 2005 through 3 November 2005
ER -