摘要
This paper presents a scan design for asynchronous sequential logic circuits (ASLCs) using modified SR-latches. With this scan structure, an ASLC is operated in an asynchronous way during the normal operation mode, while it is synchronized with clock signals during the test mode. The modified SR-latch is free of hazards and races for both fault-free and faulty circuits and the scan structure is race-free during normal operation and test modes. The structure achieves full testability of all single stuck-at faults.
| 原文 | English |
|---|---|
| 主出版物標題 | Midwest Symposium on Circuits and Systems |
| 發行者 | Publ by IEEE |
| 頁面 | 1300-1303 |
| 頁數 | 4 |
| ISBN（列印） | 0780317610 |
| 出版狀態 | Published - 1993 十二月 1 |
| 事件 | Proceedings of the 36th Midwest Symposium on Circuits and Systems - Detroit, MI, USA 持續時間: 1993 八月 16 → 1993 八月 18 |
出版系列
| 名字 | Midwest Symposium on Circuits and Systems |
|---|---|
| 卷 | 2 |
Other
| Other | Proceedings of the 36th Midwest Symposium on Circuits and Systems |
|---|---|
| 城市 | Detroit, MI, USA |
| 期間 | 93-08-16 → 93-08-18 |
指紋
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering
引用此文
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Scan design for asynchronous sequential logic circuits using SR-latches. / Shieh, Ming-Der; Wey, Chin Long; Fisher, P. David.
Midwest Symposium on Circuits and Systems. Publ by IEEE, 1993. p. 1300-1303 (Midwest Symposium on Circuits and Systems; 卷 2).研究成果: Conference contribution
TY - GEN
T1 - Scan design for asynchronous sequential logic circuits using SR-latches
AU - Shieh, Ming-Der
AU - Wey, Chin Long
AU - Fisher, P. David
PY - 1993/12/1
Y1 - 1993/12/1
N2 - This paper presents a scan design for asynchronous sequential logic circuits (ASLCs) using modified SR-latches. With this scan structure, an ASLC is operated in an asynchronous way during the normal operation mode, while it is synchronized with clock signals during the test mode. The modified SR-latch is free of hazards and races for both fault-free and faulty circuits and the scan structure is race-free during normal operation and test modes. The structure achieves full testability of all single stuck-at faults.
AB - This paper presents a scan design for asynchronous sequential logic circuits (ASLCs) using modified SR-latches. With this scan structure, an ASLC is operated in an asynchronous way during the normal operation mode, while it is synchronized with clock signals during the test mode. The modified SR-latch is free of hazards and races for both fault-free and faulty circuits and the scan structure is race-free during normal operation and test modes. The structure achieves full testability of all single stuck-at faults.
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UR - http://www.scopus.com/inward/citedby.url?scp=0027710390&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:0027710390
SN - 0780317610
T3 - Midwest Symposium on Circuits and Systems
SP - 1300
EP - 1303
BT - Midwest Symposium on Circuits and Systems
PB - Publ by IEEE
ER -