Scan design for asynchronous sequential logic circuits using SR-latches

Ming-Der Shieh, Chin Long Wey, P. David Fisher

研究成果: Conference contribution

6 引文 (Scopus)

摘要

This paper presents a scan design for asynchronous sequential logic circuits (ASLCs) using modified SR-latches. With this scan structure, an ASLC is operated in an asynchronous way during the normal operation mode, while it is synchronized with clock signals during the test mode. The modified SR-latch is free of hazards and races for both fault-free and faulty circuits and the scan structure is race-free during normal operation and test modes. The structure achieves full testability of all single stuck-at faults.

原文English
主出版物標題Midwest Symposium on Circuits and Systems
發行者Publ by IEEE
頁面1300-1303
頁數4
ISBN(列印)0780317610
出版狀態Published - 1993 十二月 1
事件Proceedings of the 36th Midwest Symposium on Circuits and Systems - Detroit, MI, USA
持續時間: 1993 八月 161993 八月 18

出版系列

名字Midwest Symposium on Circuits and Systems
2

Other

OtherProceedings of the 36th Midwest Symposium on Circuits and Systems
城市Detroit, MI, USA
期間93-08-1693-08-18

指紋

Asynchronous sequential logic
Sequential circuits
Flip flop circuits
Clocks
Hazards
Networks (circuits)

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

引用此文

Shieh, M-D., Wey, C. L., & Fisher, P. D. (1993). Scan design for asynchronous sequential logic circuits using SR-latches. 於 Midwest Symposium on Circuits and Systems (頁 1300-1303). (Midwest Symposium on Circuits and Systems; 卷 2). Publ by IEEE.
Shieh, Ming-Der ; Wey, Chin Long ; Fisher, P. David. / Scan design for asynchronous sequential logic circuits using SR-latches. Midwest Symposium on Circuits and Systems. Publ by IEEE, 1993. 頁 1300-1303 (Midwest Symposium on Circuits and Systems).
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Shieh, M-D, Wey, CL & Fisher, PD 1993, Scan design for asynchronous sequential logic circuits using SR-latches. 於 Midwest Symposium on Circuits and Systems. Midwest Symposium on Circuits and Systems, 卷 2, Publ by IEEE, 頁 1300-1303, Proceedings of the 36th Midwest Symposium on Circuits and Systems, Detroit, MI, USA, 93-08-16.

Scan design for asynchronous sequential logic circuits using SR-latches. / Shieh, Ming-Der; Wey, Chin Long; Fisher, P. David.

Midwest Symposium on Circuits and Systems. Publ by IEEE, 1993. p. 1300-1303 (Midwest Symposium on Circuits and Systems; 卷 2).

研究成果: Conference contribution

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N2 - This paper presents a scan design for asynchronous sequential logic circuits (ASLCs) using modified SR-latches. With this scan structure, an ASLC is operated in an asynchronous way during the normal operation mode, while it is synchronized with clock signals during the test mode. The modified SR-latch is free of hazards and races for both fault-free and faulty circuits and the scan structure is race-free during normal operation and test modes. The structure achieves full testability of all single stuck-at faults.

AB - This paper presents a scan design for asynchronous sequential logic circuits (ASLCs) using modified SR-latches. With this scan structure, an ASLC is operated in an asynchronous way during the normal operation mode, while it is synchronized with clock signals during the test mode. The modified SR-latch is free of hazards and races for both fault-free and faulty circuits and the scan structure is race-free during normal operation and test modes. The structure achieves full testability of all single stuck-at faults.

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Shieh M-D, Wey CL, Fisher PD. Scan design for asynchronous sequential logic circuits using SR-latches. 於 Midwest Symposium on Circuits and Systems. Publ by IEEE. 1993. p. 1300-1303. (Midwest Symposium on Circuits and Systems).