TY - JOUR
T1 - Self-calibrating clock distribution with scheduled skews
AU - Hsieh, Hong Yean
AU - Liu, Wentai
AU - Clements, Mark
AU - Franzon, Paul
PY - 1998
Y1 - 1998
N2 - This paper presents a self-calibrating clock distribution scheme that dynamically compensates manufacturing and environmental variations to minimize unintentional clock skews and employs non-zero intentional skews to improve system performance. The tracking process is implemented with an all-digital phase-locked loop and has been verified through a prototype chip. Test results confirm the theoretical predictions that the absolute value of unintentional skew is limited to Δ, which is the resolution of the sampling and compensation circuitry.
AB - This paper presents a self-calibrating clock distribution scheme that dynamically compensates manufacturing and environmental variations to minimize unintentional clock skews and employs non-zero intentional skews to improve system performance. The tracking process is implemented with an all-digital phase-locked loop and has been verified through a prototype chip. Test results confirm the theoretical predictions that the absolute value of unintentional skew is limited to Δ, which is the resolution of the sampling and compensation circuitry.
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M3 - Conference article
AN - SCOPUS:0031632292
SN - 0271-4310
VL - 2
SP - 470
EP - 473
JO - Proceedings - IEEE International Symposium on Circuits and Systems
JF - Proceedings - IEEE International Symposium on Circuits and Systems
T2 - Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS. Part 5 (of 6)
Y2 - 31 May 1998 through 3 June 1998
ER -