Sensorless dead-time exploration for digitally controlled switching converters

Bo Ting Yeh, Chun Hung Yang, Kai Cheung Juang, Chien Hung Tsai

研究成果: Conference contribution

4 引文 斯高帕斯(Scopus)

摘要

This paper proposes a sensorless dead-time exploration algorithm for a synchronous switching converter. An exploration algorithm using delay-line circuits instead of high frequency circuits is used to accelerate optimal dead-time searching and provide high quantization resolution with the dead-time step. The dead-time controller utilizes the relationship between the duty-cycle command and power loss to find the optimal dead-time without sensing any power-stage signals. This approach is well suited for digital integrated circuit implementation. Experimental results show that the converter, fabricated in the 0.18-μm CMOS process, can quickly find the optimal dead-time and improve efficiency.

原文English
主出版物標題2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013
DOIs
出版狀態Published - 2013 八月 15
事件2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013 - Hsinchu, Taiwan
持續時間: 2013 四月 222013 四月 24

出版系列

名字2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013

Other

Other2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013
國家/地區Taiwan
城市Hsinchu
期間13-04-2213-04-24

All Science Journal Classification (ASJC) codes

  • 硬體和架構
  • 電氣與電子工程

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