Shallow trench isolation stress modification by optimal shallow trench isolation process for sub-65-nm low power complementary metal oxide semiconductor technology

Chan Yuan Hu, Jone-Fang Chen, Shih Chih Chen, Shoou-Jinn Chang, Shih Ming Wang, Chih Ping Lee, Kay Ming Lee

研究成果: Article

2 引文 (Scopus)

摘要

Shallow trench isolation (STI) induced mechanical stress affects the device behavior in the advanced complementary metal oxide semiconductor (CMOS) technology. This article presents how to use an optimal STI process to reduce transistor mismatch and leakage current induced standby current in static random access memory (SRAM). The STI induced mechanical stress affects the device behavior in the advanced CMOS technology. The optimized STI process can reduce junction and bulk leakage that occurs on the STI sidewall due to STI compressive stress enhancing boron diffusion and increasing junction electric field of STI sidewall resulting in band-to-band-tunneling (BTBT) degradation. An obvious decrease in BTBT occurs on STI edge sidewall that is observed by using the optimized STI process. Meanwhile, the optimized STI process has better length of diffusion effect. Moreover, the optimized STI process can improve the parasitic device at STI edge because of smaller divot. Since random fluctuation of channel dopant and process induced device mismatch are major considerations in SRAM cell, we examine STI sidewall boron dopant diffusion effect on SRAM due to BTBT increasing exponentially with increasing doping concentration in the P -well of negative metal oxide semiconductor field effect transistor. The mismatch of passing gate of SRAM and Vccmin can also be improved by leakage reduction from the optimized STI process due to improved random dopant fluctuation.

原文English
頁(從 - 到)391-397
頁數7
期刊Journal of Vacuum Science and Technology B:Nanotechnology and Microelectronics
28
發行號2
DOIs
出版狀態Published - 2010 一月 1

指紋

isolation
CMOS
Metals
Doping (additives)
Data storage equipment
Boron
random access memory
MOSFET devices
Compressive stress
Leakage currents
Transistors
Electric fields
leakage
Degradation
Oxide semiconductors
boron
metal oxide semiconductors
transistors
field effect transistors
degradation

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Instrumentation
  • Process Chemistry and Technology
  • Surfaces, Coatings and Films
  • Electrical and Electronic Engineering
  • Materials Chemistry

引用此文

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abstract = "Shallow trench isolation (STI) induced mechanical stress affects the device behavior in the advanced complementary metal oxide semiconductor (CMOS) technology. This article presents how to use an optimal STI process to reduce transistor mismatch and leakage current induced standby current in static random access memory (SRAM). The STI induced mechanical stress affects the device behavior in the advanced CMOS technology. The optimized STI process can reduce junction and bulk leakage that occurs on the STI sidewall due to STI compressive stress enhancing boron diffusion and increasing junction electric field of STI sidewall resulting in band-to-band-tunneling (BTBT) degradation. An obvious decrease in BTBT occurs on STI edge sidewall that is observed by using the optimized STI process. Meanwhile, the optimized STI process has better length of diffusion effect. Moreover, the optimized STI process can improve the parasitic device at STI edge because of smaller divot. Since random fluctuation of channel dopant and process induced device mismatch are major considerations in SRAM cell, we examine STI sidewall boron dopant diffusion effect on SRAM due to BTBT increasing exponentially with increasing doping concentration in the P -well of negative metal oxide semiconductor field effect transistor. The mismatch of passing gate of SRAM and Vccmin can also be improved by leakage reduction from the optimized STI process due to improved random dopant fluctuation.",
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AU - Chen, Shih Chih

AU - Chang, Shoou-Jinn

AU - Wang, Shih Ming

AU - Lee, Chih Ping

AU - Lee, Kay Ming

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