Unlike MOSFETs, tunnel-FETs (TFETs) are not limited by a 60 mV/dec subthreshold swing and therefore scaling the supply voltage beyond the MOSFET's 1 V plateau becomes feasible. Supply voltage scaling is a necessary condition for reducing the power consumption per transistor, which enables further size scaling of the FETs. Designing a successful FET is however challenging, because it is not sufficient for the TFET to realize a sub-60 mV/dec subthreshold swing at one particular voltage. The next-generation FET must realize an average sub-60 mV/dec subthreshold swing over the whole supply voltage window, such that on-currents of about Ion = 100 μA/μm are achieved with I on/Ioff ratios of about 106 for sub 0.5 V supply voltages. Silicon-based TFETs are the most attractive because they allow for a full re-use of the existing expertise in fabricating silicon MOSFETs. However, the large bandgap of silicon (Si) results in low on-currents for the all-Si TFET and both input and output characteristics are inferior to the ones of all-Si MOSFETs.