Silicon germanium FinFET device physics, process integration and modeling considerations (invited)

Darsen Lu, Pierre Morin, Bhagawan Sahu, Terence B. Hook, Pouya Hashemi, Andreas Scholze, Bomsoo Kim, Pranita Kerber, Ali Khakifirooz, Phil Oldiges, Ken Rim, Bruce Doris

研究成果: Conference article同行評審

11 引文 斯高帕斯(Scopus)

摘要

We introduce SiGe FinFET device physics, process integration, and modeling considerations. Germanium is know to have a higher hole mobility than silicon. Enhancement of hole velocity due to lattice mismatch strain in SiGe epitaxy layers is significant. In addition, uniaxial stress is beneficial for device performance. Transformation of biaxial to uniaxial stress naturally occurs when SiGe film is etched into stripes. Furthermore, control of MOSFET threshold voltage by adjusting the SiGe-channel germanium content is possible. On the other hand, SiGe processing challenges include the elimination of interface trap states at the gate dielectric interface, fast diffusion of n-type dopants, and defects in stress relaxed buffer and critical thickness limitations. Band-to-band tunneling sets a lower bound to device static leakage current.

原文English
頁(從 - 到)337-345
頁數9
期刊ECS Transactions
64
發行號6
DOIs
出版狀態Published - 2014
事件6th SiGe, Ge, and Related Compounds: Materials, Processing and Devices Symposium - 2014 ECS and SMEQ Joint International Meeting - Cancun, Mexico
持續時間: 2014 十月 52014 十月 9

All Science Journal Classification (ASJC) codes

  • 工程 (全部)

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