Simulation-based study of high-density SRAM voltage scaling enabled by inserted-oxide FinFET technology

Yi Ting Wu, Fei Ding, Daniel Connelly, Meng Hsueh Chiang, Jone F. Chen, Tsu Jae King Liu

研究成果: Article同行評審

1 引文 斯高帕斯(Scopus)

摘要

A scheme for precisely adjusting the drive strength of an inserted-oxide FinFET (iFinFET) comprising two nanowire (NW) channel regions that are separated by a thin oxide layer, to enhance the manufacturing yield of a minimally sized six-transistor static random access memory (6T-SRAM) cell, is investigated in this paper. The 3-D process simulations show that the upper NW channel region can be selectively rendered nonconducting by dopant ion implantation followed by thermal annealing so that its threshold voltage is greater than the supply voltage (VDD). Furthermore, the position of the inserted-oxide layer can be adjusted to balance the tradeoff between the read stability and write-ability to achieve the lowest minimum cell operating voltage (Vmin). Using a compact transistor model calibrated to 3-D device simulations, doped iFinFET technology is projected to enable Vmin of a minimally sized 6T-SRAM cell to be substantially lower than VDD, eliminating the need for write-assist circuitry and lowering power consumption.

原文English
文章編號8661752
頁(從 - 到)1754-1759
頁數6
期刊IEEE Transactions on Electron Devices
66
發行號4
DOIs
出版狀態Published - 2019 四月

All Science Journal Classification (ASJC) codes

  • 電子、光磁材料
  • 電氣與電子工程

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