Simulation-Based Study of High-Permittivity Inserted-Oxide FinFET with Low-Permittivity Inner Spacers

Yi Ting Wu, Meng Hsueh Chiang, Jone F. Chen, Tsu Jae King Liu

研究成果: Article同行評審

摘要

A high-permittivity (high- ${k}$ ) inserted-oxide FinFET (iFinFET) structure with low-permittivity inner spacers is proposed for CMOS transistor scaling to the 3-nm technology node and beyond. The process to fabricate an iFinFET is similar to the process to fabricate a nanosheet field-effect transistor (NSFET); no additional lithography masks are needed. Unlike the NSFET and the nanowire field-effect transistor (NWFET), which each require significant spacing between the nanosheets or nanowires (NWs) to accommodate metallic gate and dielectric insulator multilayer stacks, the iFinFET requires only a single ultrathin high- ${k}$ inserted-oxide (i-oxide) layer between the NWs, allowing more NWs to be vertically stacked within the constraint of a maximum total channel height. The i-oxide layers serve to allow fringing electric fields from the gate to penetrate into the NWs to achieve improved electrostatic integrity. Simulated performance characteristics of the proposed iFinFET structure are compared against those for the FinFET, NWFET, and NSFET. The iFinFET is projected to achieve the best electrical performance when the footprint (device layout width) is less than 80 nm.

原文English
頁(從 - 到)5529-5534
頁數6
期刊IEEE Transactions on Electron Devices
68
發行號11
DOIs
出版狀態Published - 2021 十一月 1

All Science Journal Classification (ASJC) codes

  • 電子、光磁材料
  • 電氣與電子工程

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