Simulation-Based Study of Hybrid Fin/Planar LDMOS Design for FinFET-Based System-on-Chip Technology

Yi Ting Wu, Fei Ding, Daniel Connelly, Peng Zheng, Meng Hsueh Chiang, Jone F. Chen, Tsu Jae King Liu

研究成果: Article同行評審

28 引文 斯高帕斯(Scopus)

摘要

A hybrid fin/planar lateral double-diffused MOSFET (LDMOS) design (hybrid FET) is proposed for the high-voltage input-output devices in a FinFET-based system-on-chip (SoC) technology. 3-D technology computer-aided design simulations show that a planar drift region and a planar drain region are advantageous for higher breakdown voltage (BV) to specific on-state resistance (R on\ sp) ratio (BV2/ R on\ sp). By slightly extending the planar portion of the semiconductor active region into the gated channel region, the theoretical limit of BV2/ R on\ sp for LDMOS can be surpassed. Hybrid FETs can be fabricated using a process flow that is compatible with the state-of-art FinFET SoC technology.

原文English
文章編號8010312
頁(從 - 到)4193-4199
頁數7
期刊IEEE Transactions on Electron Devices
64
發行號10
DOIs
出版狀態Published - 2017 10月

All Science Journal Classification (ASJC) codes

  • 電子、光磁材料
  • 電氣與電子工程

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