Although there are well known test algorithms that have been used by the industry for years for testing semiconductor random-access memories (RAMs), systematic evaluation of their effectiveness and efficiency has been a difficult job. In the past, it was mainly done manually by proving a certain algorithm can detect a certain type of fault. As memory technology keeps innovating, the growing complexity of the memories and number of fault types that need to be covered will require more effective and efficient test algorithms to be discovered in much shorter time. A systematic approach for developing and evaluating memory test algorithms is thus desired. We propose such an approach here: test algorithm generation by simulation (TAGS), which generates, and optimizes test algorithms, given a test time budget. Experimental results show that the algorithms generated by TAGS are more efficient than the traditional test algorithms. Using TAGS, a series of test algorithms with a detailed list of faults covered by each algorithm can be generated, providing easy trade-off between test time and fault coverage.
|出版狀態||Published - 2000 一月 1|
|事件||18th IEEE VLSI Test Symposium (VTS-2000) - Montreal, Que, Can|
持續時間: 2000 四月 30 → 2000 五月 4
|Conference||18th IEEE VLSI Test Symposium (VTS-2000)|
|城市||Montreal, Que, Can|
|期間||00-04-30 → 00-05-04|
All Science Journal Classification (ASJC) codes