Simulation-based test algorithm generation for random access memories

Chi Feng Wu, Chih Tsun Huang, Kuo Liang Cheng, Cheng Wen Wu

研究成果: Paper同行評審

39 引文 斯高帕斯(Scopus)

摘要

Although there are well known test algorithms that have been used by the industry for years for testing semiconductor random-access memories (RAMs), systematic evaluation of their effectiveness and efficiency has been a difficult job. In the past, it was mainly done manually by proving a certain algorithm can detect a certain type of fault. As memory technology keeps innovating, the growing complexity of the memories and number of fault types that need to be covered will require more effective and efficient test algorithms to be discovered in much shorter time. A systematic approach for developing and evaluating memory test algorithms is thus desired. We propose such an approach here: test algorithm generation by simulation (TAGS), which generates, and optimizes test algorithms, given a test time budget. Experimental results show that the algorithms generated by TAGS are more efficient than the traditional test algorithms. Using TAGS, a series of test algorithms with a detailed list of faults covered by each algorithm can be generated, providing easy trade-off between test time and fault coverage.

原文English
頁面291-296
頁數6
出版狀態Published - 2000 一月 1
事件18th IEEE VLSI Test Symposium (VTS-2000) - Montreal, Que, Can
持續時間: 2000 四月 302000 五月 4

Conference

Conference18th IEEE VLSI Test Symposium (VTS-2000)
城市Montreal, Que, Can
期間00-04-3000-05-04

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

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