TY - GEN
T1 - Single-Axis Capacitive Accelerometer Chip with AC Offset Suppression Loop
AU - Chiu, Heng Yu
AU - Tseng, Shih Meng
AU - Chen, Yi Chen
AU - Wei, Chia Ling
N1 - Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - A single-axis capacitive accelerometer chip with AC offset voltage cancellation function is proposed, and it consists of the front-end MEMS acceleration sensor and the back-end CMOS signal processing circuits. In fact, an AC offset suppression loop is proposed to cancel the AC offset voltage originated from the initial capacitance mismatches of the MEMS acceleration sensor. The proposed chip was fabricated by using TSMC 0.35μm2P4M mixed-signal standard CMOS process and MEMS post process. Including pads, the chip area is 2.43× 2.07mm2, and the measured sensitivity is 120.4 mVpp/g within the ± 9g sensing range.
AB - A single-axis capacitive accelerometer chip with AC offset voltage cancellation function is proposed, and it consists of the front-end MEMS acceleration sensor and the back-end CMOS signal processing circuits. In fact, an AC offset suppression loop is proposed to cancel the AC offset voltage originated from the initial capacitance mismatches of the MEMS acceleration sensor. The proposed chip was fabricated by using TSMC 0.35μm2P4M mixed-signal standard CMOS process and MEMS post process. Including pads, the chip area is 2.43× 2.07mm2, and the measured sensitivity is 120.4 mVpp/g within the ± 9g sensing range.
UR - http://www.scopus.com/inward/record.url?scp=85142513178&partnerID=8YFLogxK
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U2 - 10.1109/ISCAS48785.2022.9937688
DO - 10.1109/ISCAS48785.2022.9937688
M3 - Conference contribution
AN - SCOPUS:85142513178
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 2397
EP - 2400
BT - IEEE International Symposium on Circuits and Systems, ISCAS 2022
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2022 IEEE International Symposium on Circuits and Systems, ISCAS 2022
Y2 - 27 May 2022 through 1 June 2022
ER -