TY - JOUR
T1 - Single-Bin DFT-Based Digital Calibration Technique for CDAC in SAR ADCs
AU - Lee, Shuenn Yuh
AU - Tsou, Chieh
AU - Li, Yu Cheng
N1 - Funding Information:
Manuscript received April 2, 2019; revised June 20, 2019 and July 23, 2019; accepted August 19, 2019. Date of publication September 19, 2019; date of current version December 6, 2019. This work was supported in part by the Taiwan Semiconductor Research Institute, in part by the Ministry of Science and Technology (MOST), Taiwan, under Grant MOST 107-2218-E-006-034, Grant MOST 108-2622-8-006-004-TE2, and Grant MOST 107-2514-S-006-008, in part by Southern Taiwan Science Park, Taiwan, under Grant AZ-13-05-28-107, and in part by Nuvoton Technology Corporation. This article was recommended by Associate Editor H. Zhang. (Corresponding author: Shuenn-Yuh Lee.) The authors are with the Department of Electrical Engineering, National Cheng Kung University, Tainan 701, Taiwan (e-mail: ieesyl@ mail.ncku.edu.tw; chiehtsou6021@gmail.com; panda30186@hotmail.com).
Funding Information:
This work was supported in part by the Taiwan Semiconductor Research Institute, in part by the Ministry of Science and Technology (MOST), Taiwan, under Grant MOST 107-2218-E-006-034, Grant MOST 108-2622-8-006-004-TE2, and Grant MOST 107-2514-S-006-008, in part by Southern Taiwan Science Park, Taiwan, under Grant AZ-13-05-28-107, and in part by Nuvoton Technology Corporation.
Publisher Copyright:
© 2004-2012 IEEE.
PY - 2019/12
Y1 - 2019/12
N2 - A 1024-point single-bin discrete Fourier transform (SBDFT)-based digital calibration technique is presented for high-performance, full-code successive approximation (SAR) analog-to-digital converters (ADCs). This proposed method can evaluate the radix error in capacitor-DAC (CDAC), which deviates from the designed value. Thus, the corrected digital output codes are generated to compensate the error, thereby reducing the harmonic distortion caused by capacitor mismatch. Moreover, the proposed algorithm adopts a recursive SBDFT computation rather than a conventional fast Fourier transform (FFT) computation methods because the simple hardware, which reduces hardware complexity and power consumption, can be achieved to calculate a certain bin in this work. The effective number of bits (ENOB) and signal-to-noise ratio (SNDR) can be enhanced by approximately 2 bits and 14.52 dB, respectively, on the basis of the simulation result of a 12-bit SAR ADC behavior model with 0.3% capacitor mismatch. The proposed SAR ADC is fabricated in TSMC 0.18μ m 1P6M technology. Measurement results explain that the SNDR, spurious free dynamic range, and ENOB are 46.49/67.28 dB, 49.66/80.73 dB, and 7.43/10.88 bits before/after calibration, respectively, wherein the power supply is 3.3 V and the input signal frequency is 2 kHz with a sampling rate of 100 kS/s.
AB - A 1024-point single-bin discrete Fourier transform (SBDFT)-based digital calibration technique is presented for high-performance, full-code successive approximation (SAR) analog-to-digital converters (ADCs). This proposed method can evaluate the radix error in capacitor-DAC (CDAC), which deviates from the designed value. Thus, the corrected digital output codes are generated to compensate the error, thereby reducing the harmonic distortion caused by capacitor mismatch. Moreover, the proposed algorithm adopts a recursive SBDFT computation rather than a conventional fast Fourier transform (FFT) computation methods because the simple hardware, which reduces hardware complexity and power consumption, can be achieved to calculate a certain bin in this work. The effective number of bits (ENOB) and signal-to-noise ratio (SNDR) can be enhanced by approximately 2 bits and 14.52 dB, respectively, on the basis of the simulation result of a 12-bit SAR ADC behavior model with 0.3% capacitor mismatch. The proposed SAR ADC is fabricated in TSMC 0.18μ m 1P6M technology. Measurement results explain that the SNDR, spurious free dynamic range, and ENOB are 46.49/67.28 dB, 49.66/80.73 dB, and 7.43/10.88 bits before/after calibration, respectively, wherein the power supply is 3.3 V and the input signal frequency is 2 kHz with a sampling rate of 100 kS/s.
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U2 - 10.1109/TCSI.2019.2938242
DO - 10.1109/TCSI.2019.2938242
M3 - Article
AN - SCOPUS:85076378597
SN - 1057-7122
VL - 66
SP - 4582
EP - 4591
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
IS - 12
M1 - 8844980
ER -