Single bit-line 8T SRAM cell with asynchronous dual word-line control for bitinterleaved ultra-low voltage operation

Chi Ray Huang, Lih Yih Chiou

研究成果: Article同行評審

2 引文 斯高帕斯(Scopus)

摘要

This study proposes a single bit-line and disturbance-free static random-access memory (SRAM) cell for ultra-low voltage applications. SRAM cell with read-decoupled and cross-point structure addresses both the read-disturb and half-select stability issues; nevertheless, the write-ability is degraded due to the stacked pass transistors. In this study, the authors propose a single-ended 8T bit-cell and dual word-line control technique that can simultaneously improve the read stability, half-select stability, and write-ability without additional peripheral circuits, which is advantageous for bit-interleaved ultra-low voltage operations. A 4 kb test chip was implemented in a 90 nm complementary metal-oxide-semiconductor process to verify the proposed design. Silicon measurements indicate that the proposed design can operate at a voltage as low as 360 mV with 2.68 μW power consumption.

原文English
頁(從 - 到)713-719
頁數7
期刊IET Circuits, Devices and Systems
12
發行號6
DOIs
出版狀態Published - 2018 十一月 1

All Science Journal Classification (ASJC) codes

  • Control and Systems Engineering
  • Electrical and Electronic Engineering

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