Software-based self-test (SBST) is a promising approach for testing a processor core embedded in a system-on-chip (SoC) system. Test routine development for SBST can be based on information of different abstraction levels. Multilevel abstraction-based SBST develops the test program for a pipeline processor using the information abstracted from its architecture model, register transfer level (RTL) descriptions, and gate-level netlist for different types of processor circuits. The proposed methodology uses gate-level and architecture information to improve coverage for structural faults. This SBST methodology uses an automatic test pattern generation tool to generate the constrained test patterns to effectively test the combinational fundamental intellectual properties used in the processor. The approach refers to the RTL code and processor architecture for the rest of the control and steering logic for test routine development. The effectiveness of this SBST methodology is demonstrated by the achieved fault coverage, test program size, and testing cycle count on a complex pipeline processor core. Comparisons with previous works are also made.
|頁（從 - 到）||505-517|
|期刊||IEEE Transactions on Very Large Scale Integration (VLSI) Systems|
|出版狀態||Published - 2007 5月|
All Science Journal Classification (ASJC) codes