摘要
This paper proposes vertically stacked gate-all-around MOSFET structure with optimized inner spacers to provide superior gate controllability and reduce additional parasitic capacitance simultaneously. To achieve better performance, we evaluate different inner spacer lengths while tuning source/drain doping profile to keep off-state leakage current unchanged. Considering the fabrication uniformity, the key of the conceptual process flow is to etch inner spacers selectively from top to bottom channel. The proposed approach can be applied to low power and ultra-low power design for SoC application without additional mask cost.
| 原文 | English |
|---|---|
| 主出版物標題 | Proceedings of the 20th International Symposium on Quality Electronic Design, ISQED 2019 |
| 發行者 | IEEE Computer Society |
| 頁面 | 231-234 |
| 頁數 | 4 |
| ISBN（電子） | 9781728103921 |
| DOIs | |
| 出版狀態 | Published - 2019 四月 23 |
| 事件 | 20th International Symposium on Quality Electronic Design, ISQED 2019 - Santa Clara, United States 持續時間: 2019 三月 6 → 2019 三月 7 |
出版系列
| 名字 | Proceedings - International Symposium on Quality Electronic Design, ISQED |
|---|---|
| 卷 | 2019-March |
| ISSN（列印） | 1948-3287 |
| ISSN（電子） | 1948-3295 |
Conference
| Conference | 20th International Symposium on Quality Electronic Design, ISQED 2019 |
|---|---|
| 國家 | United States |
| 城市 | Santa Clara |
| 期間 | 19-03-06 → 19-03-07 |
指紋
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering
- Safety, Risk, Reliability and Quality
引用此文
}
Speed Optimization of Vertically Stacked Gate-All-Around MOSFETs with Inner Spacers for Low Power and Ultra-Low Power Applications. / Huang, Ya Chi; Chiang, Meng-Hsueh; Wang, Shui-Jinn.
Proceedings of the 20th International Symposium on Quality Electronic Design, ISQED 2019. IEEE Computer Society, 2019. p. 231-234 8697706 (Proceedings - International Symposium on Quality Electronic Design, ISQED; 卷 2019-March).研究成果: Conference contribution
TY - GEN
T1 - Speed Optimization of Vertically Stacked Gate-All-Around MOSFETs with Inner Spacers for Low Power and Ultra-Low Power Applications
AU - Huang, Ya Chi
AU - Chiang, Meng-Hsueh
AU - Wang, Shui-Jinn
PY - 2019/4/23
Y1 - 2019/4/23
N2 - This paper proposes vertically stacked gate-all-around MOSFET structure with optimized inner spacers to provide superior gate controllability and reduce additional parasitic capacitance simultaneously. To achieve better performance, we evaluate different inner spacer lengths while tuning source/drain doping profile to keep off-state leakage current unchanged. Considering the fabrication uniformity, the key of the conceptual process flow is to etch inner spacers selectively from top to bottom channel. The proposed approach can be applied to low power and ultra-low power design for SoC application without additional mask cost.
AB - This paper proposes vertically stacked gate-all-around MOSFET structure with optimized inner spacers to provide superior gate controllability and reduce additional parasitic capacitance simultaneously. To achieve better performance, we evaluate different inner spacer lengths while tuning source/drain doping profile to keep off-state leakage current unchanged. Considering the fabrication uniformity, the key of the conceptual process flow is to etch inner spacers selectively from top to bottom channel. The proposed approach can be applied to low power and ultra-low power design for SoC application without additional mask cost.
UR - http://www.scopus.com/inward/record.url?scp=85065178852&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85065178852&partnerID=8YFLogxK
U2 - 10.1109/ISQED.2019.8697706
DO - 10.1109/ISQED.2019.8697706
M3 - Conference contribution
AN - SCOPUS:85065178852
T3 - Proceedings - International Symposium on Quality Electronic Design, ISQED
SP - 231
EP - 234
BT - Proceedings of the 20th International Symposium on Quality Electronic Design, ISQED 2019
PB - IEEE Computer Society
ER -