Speed Optimization of Vertically Stacked Gate-All-Around MOSFETs with Inner Spacers for Low Power and Ultra-Low Power Applications

Ya Chi Huang, Meng Hsueh Chiang, Shui Jinn Wang

研究成果: Conference contribution

4 引文 斯高帕斯(Scopus)

摘要

This paper proposes vertically stacked gate-all-around MOSFET structure with optimized inner spacers to provide superior gate controllability and reduce additional parasitic capacitance simultaneously. To achieve better performance, we evaluate different inner spacer lengths while tuning source/drain doping profile to keep off-state leakage current unchanged. Considering the fabrication uniformity, the key of the conceptual process flow is to etch inner spacers selectively from top to bottom channel. The proposed approach can be applied to low power and ultra-low power design for SoC application without additional mask cost.

原文English
主出版物標題Proceedings of the 20th International Symposium on Quality Electronic Design, ISQED 2019
發行者IEEE Computer Society
頁面231-234
頁數4
ISBN(電子)9781728103921
DOIs
出版狀態Published - 2019 4月 23
事件20th International Symposium on Quality Electronic Design, ISQED 2019 - Santa Clara, United States
持續時間: 2019 3月 62019 3月 7

出版系列

名字Proceedings - International Symposium on Quality Electronic Design, ISQED
2019-March
ISSN(列印)1948-3287
ISSN(電子)1948-3295

Conference

Conference20th International Symposium on Quality Electronic Design, ISQED 2019
國家/地區United States
城市Santa Clara
期間19-03-0619-03-07

All Science Journal Classification (ASJC) codes

  • 硬體和架構
  • 電氣與電子工程
  • 安全、風險、可靠性和品質

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