Speed Optimization of Vertically Stacked Gate-All-Around MOSFETs with Inner Spacers for Low Power and Ultra-Low Power Applications

研究成果: Conference contribution

摘要

This paper proposes vertically stacked gate-all-around MOSFET structure with optimized inner spacers to provide superior gate controllability and reduce additional parasitic capacitance simultaneously. To achieve better performance, we evaluate different inner spacer lengths while tuning source/drain doping profile to keep off-state leakage current unchanged. Considering the fabrication uniformity, the key of the conceptual process flow is to etch inner spacers selectively from top to bottom channel. The proposed approach can be applied to low power and ultra-low power design for SoC application without additional mask cost.

原文English
主出版物標題Proceedings of the 20th International Symposium on Quality Electronic Design, ISQED 2019
發行者IEEE Computer Society
頁面231-234
頁數4
ISBN(電子)9781728103921
DOIs
出版狀態Published - 2019 四月 23
事件20th International Symposium on Quality Electronic Design, ISQED 2019 - Santa Clara, United States
持續時間: 2019 三月 62019 三月 7

出版系列

名字Proceedings - International Symposium on Quality Electronic Design, ISQED
2019-March
ISSN(列印)1948-3287
ISSN(電子)1948-3295

Conference

Conference20th International Symposium on Quality Electronic Design, ISQED 2019
國家United States
城市Santa Clara
期間19-03-0619-03-07

指紋

Controllability
Leakage currents
Masks
Capacitance
Tuning
Doping (additives)
Fabrication
Costs
System-on-chip

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

引用此文

Huang, Y. C., Chiang, M-H., & Wang, S-J. (2019). Speed Optimization of Vertically Stacked Gate-All-Around MOSFETs with Inner Spacers for Low Power and Ultra-Low Power Applications. 於 Proceedings of the 20th International Symposium on Quality Electronic Design, ISQED 2019 (頁 231-234). [8697706] (Proceedings - International Symposium on Quality Electronic Design, ISQED; 卷 2019-March). IEEE Computer Society. https://doi.org/10.1109/ISQED.2019.8697706
Huang, Ya Chi ; Chiang, Meng-Hsueh ; Wang, Shui-Jinn. / Speed Optimization of Vertically Stacked Gate-All-Around MOSFETs with Inner Spacers for Low Power and Ultra-Low Power Applications. Proceedings of the 20th International Symposium on Quality Electronic Design, ISQED 2019. IEEE Computer Society, 2019. 頁 231-234 (Proceedings - International Symposium on Quality Electronic Design, ISQED).
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abstract = "This paper proposes vertically stacked gate-all-around MOSFET structure with optimized inner spacers to provide superior gate controllability and reduce additional parasitic capacitance simultaneously. To achieve better performance, we evaluate different inner spacer lengths while tuning source/drain doping profile to keep off-state leakage current unchanged. Considering the fabrication uniformity, the key of the conceptual process flow is to etch inner spacers selectively from top to bottom channel. The proposed approach can be applied to low power and ultra-low power design for SoC application without additional mask cost.",
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Huang, YC, Chiang, M-H & Wang, S-J 2019, Speed Optimization of Vertically Stacked Gate-All-Around MOSFETs with Inner Spacers for Low Power and Ultra-Low Power Applications. 於 Proceedings of the 20th International Symposium on Quality Electronic Design, ISQED 2019., 8697706, Proceedings - International Symposium on Quality Electronic Design, ISQED, 卷 2019-March, IEEE Computer Society, 頁 231-234, 20th International Symposium on Quality Electronic Design, ISQED 2019, Santa Clara, United States, 19-03-06. https://doi.org/10.1109/ISQED.2019.8697706

Speed Optimization of Vertically Stacked Gate-All-Around MOSFETs with Inner Spacers for Low Power and Ultra-Low Power Applications. / Huang, Ya Chi; Chiang, Meng-Hsueh; Wang, Shui-Jinn.

Proceedings of the 20th International Symposium on Quality Electronic Design, ISQED 2019. IEEE Computer Society, 2019. p. 231-234 8697706 (Proceedings - International Symposium on Quality Electronic Design, ISQED; 卷 2019-March).

研究成果: Conference contribution

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Huang YC, Chiang M-H, Wang S-J. Speed Optimization of Vertically Stacked Gate-All-Around MOSFETs with Inner Spacers for Low Power and Ultra-Low Power Applications. 於 Proceedings of the 20th International Symposium on Quality Electronic Design, ISQED 2019. IEEE Computer Society. 2019. p. 231-234. 8697706. (Proceedings - International Symposium on Quality Electronic Design, ISQED). https://doi.org/10.1109/ISQED.2019.8697706