SRAM delay fault modeling and test algorithm development

Rei Fu Huang, Yan Ting Lai, Yung Fa Chou, Cheng Wen Wu

研究成果: Paper同行評審

4 引文 斯高帕斯(Scopus)

摘要

With the advent of deep-submicron VLSI technologies, the working speed of SRAM circuits has grown to a level that at-speed testing of SRAM has become an important issue. In this paper, we present delay fault models for SRAM, i.e., the faults that affect the access time of the SRAM circuit. We also develop the test algorithm that detects these faults. The proposed SRAM delay-fault test algorithm has a complexity of 3N + 2k Read/Write operations, where N is the number of words and k is the word count in a row.

原文English
頁面104-109
頁數6
出版狀態Published - 2004 六月 1
事件Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004 - Yokohama, Japan
持續時間: 2004 一月 272004 一月 30

Conference

ConferenceProceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004
國家Japan
城市Yokohama
期間04-01-2704-01-30

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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